TL494 - magic chip, Part 6
While testing this device, do not overload, do not load asymmetrically. For checking your system, remove nixie and load secondary winding of transformer with simple resistor.
Download small (~500kb XVid AVI): with oscillograms. And now take a note, that on the “drain" oscillogram you see other phase pulses. Even when mosfet if in off stage, the induction from other primary winding cause voltage to appear. This may kill mosfet. And if load is unbalanced or not ideal, you can find lots of parasitic oscillations. So design engineer must take care of them. Parasitic oscillations can be killed with “snublers"- simple RC network on transformer windings. This devices takes some of the high frequency power and dissipates it.
And now lets look in internet:
Half-bridge and full-bridge |
Push-pull |
Forward converter |
|
minimum mosfet voltage rating |
supply voltage plus a safety margin
230VAC*1,414 + 50V |
double the supply voltage plus a large safety margin 2*230VAC*1,414+100V |
double the supply voltage plus a large safety margin 2*230VAC*1,414+100V |
other mosfet properties |
medium voltage 400V fets, so a <0.2 Ohm channel resistance is typical => high current, low loss |
high voltage 800V fets, >2.0 Ohm channel resistance is typical => low current, high loss |
high voltage 800V fets, >2.0 Ohm channel resistance is typical => low current, high loss |
mosfet body diode: |
must be disabled, otherwise mosfets explode if supply <50VDC: if supply >50VDC: |
can be ignored |
can be ignored |
realistic power levels |
many kW |
some 100W |
some 100W |
what limits the power level |
base-feed transformer core power handling capability (saturation, induced currents causing core heating) mosfet current ratings (paralleling more than two fets, the right way, mosfet switching and conduction losses |
primary leakage inductance, huge voltage spikes (up to kV range) at increasing power levels, makes use of snubber circuits imperative (=>high heating losses and low efficiency, and high circuit complexity) >=800V fets are expensive and can't handle much current |
(same as for push-pull) |
transformer design |
needs only one primary transformer design non-critical |
needs two identical and well coupled primaries, critical design - requires skills! ;o) |
critical design, only one primary only the first quadrant of the ferrite cores' B-H curve is used, i.e. |
base feed transformer volt-seconds (Vs) imbalance: |
full-bridge: minimal danger of saturation, Vs imbalance mainly due to slight differences in mosfet channel on-resistances half-bridge: if the primary has a series coupling capacitor, then Vs |
major problems with Vs imbalance as fully identical pri windings are almost impossible to make. The driver circuit absolutely must have pulse-by-pulse current limiting. |
|
tuneable down to DC / 0Hz |
yes, by using a primary series coupling capacitor |
no (short-circuit at 0 Hz) |
no (short-circuit at freq towards 0 Hz) |
problems |
grief with gate drive transformers or floating channel mosfet driver ICs or optocoupler-tweaking |
grief with mosfets constantly dying on overvoltage, gate drive noise |
(same as for push-pull) |
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